The present invention relates to main memories of data processing systems and more particularly to those memories provided with devices which improve their reliability and are capable of detecting and correcting errors caused by failure of the memory circuits. The advent of LSI semiconductor circuit technology has led to the progressive replacement of magnetic core memories by semiconductor integrated circuit memories.
These devices, besides having a very low cost per stored information unit, offer the advantage of an extremely reduced size and are suitable for fabricating memories having very high storage capacities. Although the degree of reliability provided by such semiconductor circuits is high, a certain probability of failures occurring within these integrated devices either at initialization time or during operation time still exists. Such failures may influence the accuracy of information stored in or read from particular memory locations. The failure probability, while low for a single integrated device, may nonetheless become appreciable in the case of a large capacity memory comprising a considerable number of integrated devices.
This factor has led to the utilization of redundancy storage techniques in which it is possible to identify and correct errors, thus allowing effective utilization of memory devices even in the event of circuit failures that would cause erroneous writing and reading operations in a non-redundant memory. Today, among the different redundency systems commonly employed, the more convenient employ error correcting codes, the so called SEC-DED (Single Error Correction--Double Error Detection) codes are the ones most commonly used and provide detection and correction of single bit errors in the read out data and detection, but not correction, of double bit errors in the readout data.
A description of the theory on which these codes and the devices utilizing them are based, is omitted here since it is not essential for an understanding of the invention; furthermore a large amount of literature has been published, beginning with R. W. Hamming's article: "Error Detecting and Error Detecting Code," published in the Bell System Technical Journal, Vol. XXII, No. 2, April 1950.
The use of such codes requires that, in storing a binary coded data byte, the error correcting code associated with the byte must be generated and then stored in the memory along with the byte. Likewise, it is necessary, before using information read out from the memory, to process it by generating the related code and comparing it with the one already stored and read out with the information. From this comparison an error condition may result which, through a correction network, leads, if necessary, to the correction of the readout information. These operations of correction code generation, correction code regeneration on readout, comparison, and correction, if necessary, are performed by means of logical circuits which have a certain, non-negligible intervention time.
In the case of error code generation during a write operation in memory, the generation time and the time required for memory addressing may overlap, consequently no delay is added. However, in the case of error code regeneration and comparison during a read operation, the necessary functions can be performed only after the reading has been completed, whereupon the validation process imposes a certain delay time on memory readout operations. This delay may greatly hamper memory performance. Furthermore it is foreseen that in the future, with the advent of bipolar LSI integrated circuits which are intrinsically much faster than integrated circuits of the MOS type, which have been preferred for their high level of integration, the validation delay will become, as a percentage of readout time, even more detrimental.